1. Technical Field
The present invention relates to an active matrix type TFT array substrate on which a thin film transistor (hereinafter referred to as TFT) is mounted to serve as a switching element, to a liquid crystal display using the TFT array substrate, and to a manufacturing method of them.
2. Background Art
Researches and developments of liquid crystal display to serve as a flat panel display in substitution for CRT have been popularly carried out. In particular, making use of its feature of small power consumption and small thickness, several liquid crystal displays have been heretofore put into practical use to serve as a display for ultra small size television or for notebook type personal computer driven by battery. As a drive method of the liquid crystal display, an active matrix type TFT array is principally used in which TFT is used as a switching element from the viewpoint of high display quality.
To achieve small power consumption in the liquid crystal display, it is effective to increase an effective display area of picture element section of the liquid crystal panel, i.e., to enhance aperture ratio of picture element. As a TFT array effective for achieving a liquid crystal panel of a high aperture ratio, for example, the Japanese Patent Publication (examined) Nos.2521752 and 2598420 and tile Japanese Laid-Open Patent Publication (unexamined) No.163528/1992, etc. disclose a structure. In this structure, after forming a TFT comprising a scanning electrode, a signal electrode and a semiconductor layer, an interlayer insulating film composed of a transparent resin is formed to coat the TFT, and a picture element electrode is formed on the uppermost layer.
A high aperture ratio is achieved in the mentioned structure principally by following two reasons. In the first place, as the picture element electrode is formed on the interlayer insulating film of transparent resin of which surface is flattened, it is possible to prevent a deficient display (domain phenomenon) caused by irregular orientation of liquid crystal molecules occurring at the step portion of the picture element electrode of the conventional structure, whereby it becomes possible to increase an effective display area. In the second place, by forming the picture element electrode on the relatively thick interlayer insulating film of 0.3 .mu.m to 2 .mu.m in thickness, no electric short circuit takes place between the scanning line or signal line located at the lower layer of the interlayer insulating film and the picture element electrode located on the upper layer, and therefore it becomes possible to form the picture element electrode in wider area to overlap those lines.
A manufacturing process of the mentioned known TFT array of high aperture ratio is hereinafter described. First, a TFT comprising gate electrode, gate insulating film, semiconductor layer, source electrode, and drain electrode is formed on a transparent insulating substrate such as glass substrate. Then, an interlayer insulating film composed of a transparent resin of which surface is flattened so as not to produce any step caused by the TFT is formed, and a contact hole is formed at required portions. Finally, a picture element electrode composed of a transparent conductive film such as ITO is formed, thus a TFT array being completed. The picture element electrode is electrically connected to the drain electrode on the lower layer through the contact hole formed in the interlayer insulating film.
As described in the Japanese Laid-Open Patent Publications (unexamined) Nos.127553/1997 and 152625/1997, methods for forming a contact hole in the interlayer insulating film are classified into one method in which a photosensitive transparent resin (having a photo-sensitivity) is used, and into another method in which non-photosensitive transparent resin (having no photosensitivity) is used. In the case of using a photosensitive transparent resin, a required contact hole is formed by a photomechanical process, without using any resist, in which exposure and development are performed using a mask pattern of the contact hole after application and baking of the resin. On the other hand, in the case of using a non-photosensitive transparent resin, after applying and baking the resin, a resist is applied. Then, after forming a contact pattern by photomechanical process, a dry etching is performed using a gas containing at least one of CF.sub.4, CF.sub.3 or SF.sub.6, and finally by removing the resist, a required contact hole is achieved.
On the mentioned TFT array substrate, terminals 15 electrically connected to each of the date line, the source lines, etc. are arranged on the periphery of the image display section, whereby a terminal region for connecting each terminal to an external terminal is formed. FIG. 18 is a partially top view showing an active matrix type TFT array substrate of high aperture ratio according to the prior art. In the drawing, reference numeral 1 indicates a glass substrate being a transparent insulating film, numeral 2 indicates a gate line formed on the glass substrate 1, and numeral 3 indicates a source line crossing over the gate line 2. Numeral 4 is a gate terminal electrically connected to the gate line 2, and numeral 5 is a source terminal electrically connected to the source line 3. Numeral 6 is an interlayer insulating film composed of a photosensitive transparent resin formed to cover the entire gate line 2 and source line 3 and end portions of the image display section side of the gate terminal 4 and the source terminal 5. Numeral 1 is a guard resistance, numeral 8 is a contact hole of the terminal section, and numeral 9 is a contact hole of the guard resistance section. Numeral 14 is a short ring which is formed to prevent an electrostatic destruction of the TFT at the time of manufacturing thereof, and connects electrically respective terminals to each other through the guard resistance 7.
In the active matrix type substrate of above arrangement, at the end portions on the image display section side of the gate terminal 4 and the source terminal 5, a metallic wiring on the lower layer such as gate line 2, source line 3, etc. and a transparent conductive film on the upper layer are connected to each other through the contact hole 8 formed in the interlayer insulating film 6. On the other hand, since the interlayer insulating film 6 is not formed at the end portion on the guard resistance 7 side of each terminal and at the guard resistance section 7, a photomechanical process is separately required to form, for example, the contact hole 9 in the guard resistance section.
A transparent conductive film such as ITO is used as a picture element electrode and an upper conductive film of the gate terminal 4 and the source terminal 5, and this ITO is formed by forming a film on the entire substrate and patterning the film. However, there is a difference in the manner of crystal growth and in etching speed between the ITO formed on the interlayer insulating film 6 which is an organic film and the ITO formed on the glass substrate 1 or on an inorganic film. For example, etching speed of the ITO formed on the organic film is faster than that of the ITO formed on the inorganic film by 2 to 5 times. In the actual manufacturing process, from the viewpoint of is patterning precision of the picture element electrode, it is necessary to set an etching time to that for the image display section in which the ITO is formed on the interlayer insulating film 6 composed of an organic film. Accordingly, in the terminal region on the guard resistance 7 side where the interlayer insulating film 6 is not formed, there arises a problem that the ITO remains not etched between the adjacent two gate terminals 4, and between two source terminals 5. The ITO left not etched brings about a deficient leak between respective terminals.
To reduce this deficient leak, it was necessary to perform a first etching on the etching condition (at an etching time) applied to the ITO formed on the organic film of faster etching speed, and perform a second etching at car etchsing time applied to the ITO formed on the glass substrate or on the inorganic film, while protecting the ITO on the organic film with a resist. In this manner, since it is necessary for resist pattern and etching to be performed twice, there is a disadvantage that thie manufacturing process becomes unavoidably complicated.
The Japanese Laid-Open Patent Publication (unexamined) No.90397/1997 discloses a method for etching an ITO film in which by causing an interlayer insulating film to remain between the terminals in assembly region, short circuit between the terminals can be prevented and etching process is performed once.
In the conventional liquid crystal display of above arrangement to achieve a TFT array of high aperture ratio, any interlayer insulating film is not formed in the assembly region for electrical connection between an external substrate provided on the outside of the display region of the TFT array substrate and each electrode line. Therefore, in the step of forming the picture element electrode on the interlayer insulating film, it is essential to perform twice the photomechanical process and the etching process, whereby there arise problems such that manufacturing process becomes complicated, and throughput is lowered while cost being increased.
Moreover, to leave the interlayer insulating film betweeen tile terminals, there is a further problem that irregularity due to the interlayer insulating film increases a connection resistance at the time of connecting the terminals to the external substrate.
Generally, the electrical connection between the picture element electrode of the TFT array of above structure and the drain electrode is achieved through the contact hole formed in the interlayer insulating film. In this case, to reduce the connection resistance between the picture element electrode and the drain electrode, after forming the contact hole by dry etching using CF.sub.4 +O.sub.2, SF.sub.6 +O.sub.2 or other fluorine gas+O.sub.2, an ashing process is performed using O.sub.2 gas to remove residue from the contact hole.
However, as the surface of the interlayer insulating film is also etched in the ashing process using the O.sub.2 gas, irregularity is formed on the surface of the interlayer insulating film. It was found that such a surface condition of the interlayer insulating film gives an influence on the etching characteristic (adaptability to etching) of the ITO film formed on the interlayer insulating film.
For example, after the etching process using CF.sub.4 +O.sub.2, SF.sub.6 +O.sub.2 or other fluorine gas+O.sub.2, the surface of the interlayer insulating film is smooth. When forming an ITO film on the interlayer insulating film of such a smooth condition, etching speed of the ITO film on the interlayer insulating film is almost the same as that of ITO film on the transparent insulating substrate. Thus the ITO film can be patterned by one etching process. Actually, in the case of performing an etching process at an optimum etching speed of the ITO film on the transparent insulating substrate, a side etching amount of ITO pattern on the interlayer insulating film is 1 .mu.m or less on one side, thus a desirable ITO pattern is obtained.
However, when performing the ashing process using O.sub.2 gas after the etching process using CF.sub.4 +O.sub.2, SF.sub.6 +O.sub.2 or other fluorine gas+O.sub.2, irregularity is produced on the surface of the interlayer insulating film. When forming an ITO film on the interlayer insulating film of such an irregular surface condition, etching speed of the ITO film on the interlayer insulating film is faster than that of the ITO film on the transparent insulating substrate by 5 times. Therefore, it is impossible to pattern the ITO film by just one etching process. Actually, in the case of performing an etching process at an optimum etching speed of the ITO film on the transparent insulating substrate, a side etching amount of ITO pattern on the interlayer insulating film is 3 .mu.m or more on one side, thus the ITO pattern is formed into an extremely tapered configuration.
As discussed above, in the case of performing the asliifg process with O.sub.2 gas to reduce the connection resistance between the picture element electrode and the drain electrode, there arises a problem that it is impossible to pattern the ITO film by just one etching process. On the other hand, in the case of not performing any ashing process with O.sub.2 gas, there arises another problem that the ITO film on the interlayer insulating film and the ITO film on the transparent insulating substrate can be certainly patterned by just one etching process, but connection resistance between the picture element electrode and the drain electrode is increased.